This application claims the priority benefit of Taiwan application serial no. 90109496, filed Apr. 20, 2001.
1. Field of Invention
The present invention relates to a type of programmable logic array circuit. More particularly, the present invention relates to a low power programmable logic array assembly.
2. Description of Related Art
FIG. 1 is a block diagram of a conventional programmable logic array (PLA). As shown in FIG. 1, a programmable logic array mainly includes five major blocks an input buffer 102, an AND-plane circuit 104, an inter-plane buffer 106, an OR-plane circuit 108 and an output buffer 110. The AND-plane circuit 104 and the OR-plane circuit 108 provide a sum-of-product (SOP) logic. On the other hand, the input buffer 102, the inter-plane buffer 106 and the output buffer 110 provide necessary driving capability to the logic circuit. Normally, clock control signals are included to synchronize with an outside system.
A number of improved programmable logic array designs have also been developed. The following is a brief description of some of the improved PLA circuits.
A. Conventional Clock-delayed PLA
FIG. 2 is a circuit diagram of a 5xc3x978xc3x974 conventional clock-delayed PLA. As shown in FIG. 2, the clocked-delay PLA implements the Boolean functions Z1xcx9cZ4. The xe2x80x985xe2x80x99 in the 5xc3x978xc3x974 PLA indicates that the number of input variables is five (a, b, c, d and e). The xe2x80x988xe2x80x99 in the 5xc3x978xc3x974 PLA indicates that the number of product terms is eight (P1xcx9cP8). The xe2x80x984xe2x80x99 in the 5xc3x978xc3x974 PLA indicates that the number of output values is four (Z1xcx9cZ4). Furthermore, the Boolean functions are as follows:
Z1=a{overscore (b)}{overscore (d)}e+{overscore (a)}{overscore (b)}{overscore (c)}{overscore (d)}{overscore (e)}+bc+de;xe2x80x83xe2x80x83(1)
Z2={overscore (a)}{overscore (c)}e;xe2x80x83xe2x80x83(2)
Z3=bc+de+{overscore (c)}{overscore (d)}{overscore (e)}+bd;xe2x80x83xe2x80x83(3)
Z4={overscore (a)}{overscore (c)}e+cexe2x80x83xe2x80x83(4)
In FIG. 2, an external clock control signal "psgr" produces two in-phase internal clock control signals "psgr"1 and "psgr"1d applied to the AND-plane circuit 104 and the OR-plane circuit 108 respectively. A path marked in gray color is a critical path for this circuit. A critical path is a route that includes the largest loading from an input terminal to an output terminal of the circuit and hence operating speed depends upon the critical path.
FIG. 3A is a circuit taken from the critical path in FIG. 2 and FIG. 3B is a diagram showing a set of signal waveforms related to the circuit shown in FIG. 3A. Note that the clock control signal used by the AND-plane circuit 318 and the OR-plane circuit 322 are different. If both the AND-plane circuit 318 and the OR-plane circuit 322 use the same clock control signal, signal at node 6 will be destroyed by the pre-charging signal at node 5 in the evaluation phase initialization. This will lead to data race errors shown as gray-marked area in FIG. 3B. To prevent the data race errors, clocking signal to the OR-plane circuit 322 must be delayed. One must wait until the data at node 5 is stabilized before carrying out any evaluation actions. This is the reason why this type of PLA is called a clock-delayed PLA. Hence, the main disadvantage of the clock-delayed PLA is the delay of clocking signal to the OR-plane circuit 322 to prevent data racing.
In FIG. 3B, a few time parameters are defined for analyzing operating speed of such a circuit. The following is a list of various timing definitions.
(1) External access time (tacc): from the edge of the external clock signal "psgr" rising to a high potential to the signal at the output terminal changing potential;
(2) Internal access time (tiacc): from the edge of the internal clock signal "psgr"1 rising to a high potential to the signal at the output changing potential; and
(3) Internal clocking time difference (td): time difference between the internal clock signal "psgr"1 and the internal clock signal "psgr"1d, obviously, if duty cycle of the clocking signal is 50%, the smallest operating cycle can be defined as twice the internal access time (tiacc).
As shown in FIG. 3B, the value of td can surely affect tacc and tiacc. Consequently, the critical path of a conventional clock-delayed circuit shown in FIG. 3A includes the AND function block 318, the inter-plane buffer 320, the OR function block 322 and the output buffer 324. The large parasitic capacitors CAND, Cxe2x80x2AND, Cinter, COR and Cxe2x80x2OR along the critical path is a major reason for a slow-down of the operating speed in the circuit. Due to the absence of dc power consumption in a dynamic circuit, power is dominated mainly for dynamic power consumption. In general, the power consumption of a dynamic circuit is represented by   P  =            ∑              i        =        1            n        ⁢                  α        i            ⁢              C        i            ⁢              V        DD        2            ⁢              f        .            
Here, xcex1i the switching probability of node i, Ci is the lumped capacitance of node i, VDD is the operating voltage and f is the frequency. If VDD and f has fixed values, the only consideration is the values of xcex1i and Ci. The product xcex1C is defined as the power factor (PF). The critical path shown in FIG. 3A can be used to evaluate the operating speed of the circuit. Because power consumption of the PLA circuit is related to the implemented Boolean functions, power consumption determined from the critical path is not equivalent to the power consumption of the entire circuit. To simplify estimation of power consumption, the critical path is still employed as a base with the incorporation of switching probability according to the blocks shown in FIG. 1. Because the clocking signals are global signals, clocking signal is not included into the power consumption consideration.
The following is an observation of the power factors of various functional blocks.
(1) The input buffer 102: if probability of the input signal is evenly distributed, xcex1IN can be represented by                     1        2            ·              1        2              =          1      4        ,
and power factor of the input buffer 102 is xcex1INCIN.
(2) The AND-plane circuit 104 and the inter-plane buffer region 106: if the number of input is N, the switching probability of a dynamic NOR gate is                     2        N            -      1              2      N        .
In other words, the switching probability of dynamic NOR gates in the AND-plane circuit 104 xcex1AND and xcex1xe2x80x2AND is                     2        N            -      1              2      N        .
Because the inter-plane buffer region 106 will change according to the AND-plane circuit 104, switching probability xcex1inter is             2      N        -    1        2    N  
as well. If the number of inputs is very large, the value of xcex1AND, xcex1xe2x80x2AND and 60inter is close to one. Furthermore, due to the long interconnection wires and parasitic capacitors of transistors contribute to the capacitors CAND, Cxe2x80x2AND, and Cinter, these capacitance are relatively large. Therefore, the power factors including xcex1ANDxc2x7CAND, xcex1xe2x80x2ANDxc2x7Cxe2x80x2AND, and xcex1interxc2x7Cinter of such components are a leading factor of large power consumption.
(3) The OR-plane circuit 108. The switching probability in the OR-plane circuit 108 is mainly affected by the output from the inter-plane buffer 106. Assume the OR-plane circuit 108 is an N-input dynamic NOR gate and pi is the probability of the ith input of the dynamic NOR gate being one, transition probability       α    OR    =      1    -                  ∏                  i          =          1                N            ⁢              xe2x80x83            ⁢                        (                      1            -                          p              i                                )                .            
Hence, xcex1ORxc2x7COR is related to the input and the desired function.
B. Blair""s PLA
FIG. 4A is a circuit diagram showing a Blair""s PLA and a critical path through the circuit. FIG. 4B is a timing diagram showing waveforms related to the signals in FIG. 4A. Because the AND-plane circuit 418 of the Blair""s PLA uses a pre-discharged pseudo-NMOS circuit, operating speed in the AND-plane circuit 418 is affected. Since the pseudo-NMOS circuit is a type of ratioed logic, the conductance xcex2P of PMOS transistor MP1 very small. Furthermore, the PMOS transistor MP1 needs to drive a large capacitor CAND. This often leads to a slow rising edge of signal at node 2. Such phenomenon can be observed in the gray-marked area in FIG. 4B. The critical path of the Blair""s PLA includes the AND-plane circuit 418, the inter-plane buffer 420, the OR-plane circuit 422 and the output buffer 424. One major advantage of Blair""s PLA is a reduction in dynamic power consumption so that the dynamic power is principally dominated by xcex1ORxc2x7COR. According to FIG. 4B, charges at node 2 and node 4 are discharged to ground GND in the pre-charging phase. Since the probability maintaining a low potential at node 2 and node 4 approaches 1, the value of xcex1AND and xcex1inter approaches zero. This indicates that whatever the value of the capacitor CAND and the capacitor Cinter, the value of both xcex1ANDxc2x7CAND and xcex1interxc2x7Cinter are very small. Although a Blair""s PLA can reduce dynamic power loss, dc power loss in the circuit cancels out a portion of the advantage gained. Because the AND-plane circuit 418 uses a pre-charge pseudo-NMOS circuit, the probability of the AND-plane circuit 418 turning into a pseudo-NMOS is very high within the evaluation state of the circuit. Hence, a dc current is produced in the circuit. The dc power loss is intensified as the operating frequency is lowered. In brief, one major advantage of a Blair""s PLA is a reduction in dynamic power loss. However, the advantage is often eclipsed by excessive dc power loss.
C. Dhong""s PLA
FIG. 5A is a circuit diagram showing a Dhong""s PLA and a critical path through the circuit. FIG. 5B is a timing diagram showing waveforms related to the signals in FIG. 5A. To prevent data race problem, the internal clock signal "psgr"1d must be delayed for a td until signal at node 4 is stabilized. As the internal clock signal "psgr"1d rises to a high potential, circuit within the OR-plane circuit 516 initiates an evaluation operation. Since the delay td is directly reflected in external access time, this is similar to the delay in a conventional clock-delayed PLA. In the pre-charging phase of the circuit, the capacitor CIN will discharge to a zero potential (ground GND) under the control of internal clock signals. Hence, actual input reaches node 2 only when the circuit is in the evaluation stage. This produces additional time delay leading to a longer access time. Furthermore, as the clock signal "psgr"1d in the OR-plane circuit 516 step into the evaluation phase, residual charges stored inside the capacitor Cshare start to redistribute to the capacitor COR. If all the inputs to the OR-plane circuit 516 are LOW, charge redistribution will pull node 5 to HIGH. The charge redistribution is effected by an N-type transistor. Due to body effect, rising speed at node 5 is slow. If at least one of the inputs to the OR-plane circuit 516 is at a high potential, the charges stored inside the capacitor Cshare may all leak away. In FIG. 5A, the gray-marked critical path includes a PMOS transistor 502 in the input section, the AND-plane circuit 512, the inter-plane buffer 514, the OR-plane circuit 516 and the output buffer 518. Overall length of the critical path is much longer than a conventional clock-delayed PLA and a Blair""s PLA. Note that the internal access time tiacc in this circuit is calculated from node 1 to the output point Z1.
The following is an analysis of the power factors of a Dhong""s PLA. Because Dhong""s PLA uses a special input circuit, xcex1IN, differs from a conventional clock-delayed PLA. In the pre-charging phase, the capacitors CIN is discharged to a zero potential (ground GND). Hence,       α    IN    =                    1        2            ·      1        =                  1        2            .      
In addition, the special input circuit adds parasitic capacitance to the capacitor CIN. Consequently, power consumption in the input section of the circuit will increase in proportional to the power factor xcex1INxc2x7CIN. The AND-plane circuit 512 and the inter-plane buffer 514 are functionally similar to a conventional clock-delayed circuit. The main power factors are represented by xcex1ANDxc2x7CAND and xcex1interxc2x7Cinter. These two power factors contribute significant dynamic power loss to the circuit.
The following is a discussion of the power factor of the OR-plane circuit 516. In FIG. 5A, the capacitor Cshare must have a capacitance twice that of the capacitor COR. Two principal evaluation states must be considered, namely:
(1) If a high potential is obtained at node 5 in an evaluation operation, the voltage level will rise to       2    3    ⁢            V      DD        .  
In other words,       2    3    ⁢            V      DD        ·          C      OR      
of the residual charges will be transferred to the node 5. However, the transferred electric charges will be discharged in the next pre-charging phase.
(2) If a low potential is obtained at node 5 in an evaluation operation, all the charges VDDxc2x72COR originally stored inside the capacitor Cshare will leak away. The power loss at this moment is equivalent to VDD2xc2x72CORxc2x7f. If switching probability is also includes into our consideration, from a statistical perspective, average power factor of the OR-plane circuit 516 is given by the formula:       PF    OR    =                    ∏                  i          =          1                N            ⁢              xe2x80x83            ⁢                                    (                          1              -                              p                i                                      )                    ·                      2            3                          ⁢                  C          OR                      +                            [                      1            -                                          ∏                                  i                  =                  1                                N                            ⁢                              (                                  1                  -                                      p                    i                                                  )                                              ]                ·        2            ⁢              C        OR            
Here, N is the number of inputs.  greater than From the power factor formula, power loss in the OR-plane circuit 516 of a Dhong""s PLA is larger than a conventional clock-delayed PLA. Furthermore, the special input circuit will decrease operating speed and increase additional power losses.
D. Wang""s PLA
FIG. 6A is a circuit diagram showing a Wang""s PLA and a critical path through the circuit. FIG. 6B is a timing diagram showing waveforms related to the signals in FIG. 6A. In Wang""s original design, the clocking signal for controlling the AND-plane circuit 618 and the clocking signal for controlling the OR-plane circuit 622 are identical. However, such an arrangement often leads to data race problem. In the evaluation operation 1 shown in FIG. 6B, when the clock signal "psgr"1 is at a high potential, the pair of inputs of the NAND gate 606 are at a high potential instantaneously. Ultimately, a falling and a rising glitch are produced at node 4 and 5 respectively. The upward rising glitch will switch on the dynamic gate of the OR-plane circuit 622. If the OR-plane circuit 622 gets into an evaluation state at the same time, the glitch at node 5 will produce an erroneous value. This is the so-called race problem.
To prevent race problem, the clocking signal to the OR-plane circuit 622 must be delayed until the glitch at node 5 completely disappears. In FIG. 6A, the clocking signal "psgr"1d to the OR-plane circuit 622 passes through delaying inverters 612 and 614 so that correct circuit operating sequence is ensured. This modified circuit is called an improved version of the Wang""s PLA. In the evaluation operation 2 shown in FIG. 6B, the evaluation phase of node 3 and 5 when the value is in a high potential state is considered. When node 5 rises to a level VDD and "psgr"1d is not yet in an evaluation state, the dynamic gates inside the OR-plane circuit 622 produces some dc power loss. Node 6 cannot be pulled down to a ground (GND) potential. The node 6 is pulled to the ground level only when "psgr"1d proceeds to the evaluation state. Both the improved Wang""s PLA and Dhong""s PLA both uses a special input circuit. The only difference is that the Wang""s PLA has an additional NMOS transistor 604 for producing a complete transmission gate. Hence, extra delay caused by the additional input circuit still causes an increase in the access time for the Wang""s PLA.
As shown in FIG. 6A, the critical path includes the input transmission gate 602, 604, the AND-plane circuit 618, the inter-plane buffer 620, the OR-plane circuit 622 and the output buffer 624, similar to a Dhong""s PLA. The internal access time tiacc of this circuit is also calculated from node 1 to the output point Z1. One of the most important design concept of the Wang""s PLA is centered upon the inter-plane buffer 620, an AND type inter-plane buffer 620. When the clocking signals "psgr"1 and "psgr"1d are both at a low potential, the circuit proceeds into the pre-charging phase. The nodes 3 and 6 are pre-charged to HIGH. Because one terminal of the NAND gate 606 is controlled by the clocking signal "psgr"1, node 4 in the inter-plane buffer 620 is also pre-charged to a high potential level. Consequently, node 5 is pulled down to a low potential level. When the circuit proceeds into the evaluation phase, most of the input combinations pull node 3 to the ground (GND). Thus, node 5 is maintained at a low potential level under most circumstances. This indicates that switching probability for node 5 xcex1inter is relatively small and power factor xcex1interxc2x7Cinter the inter-plane buffer 620 can be safely ignored. However, considering about the transmission delay, glitches at nodes 4 and 5 appealed on initialization of evaluation. As shown in FIG. 6B, the glitches waste a portion of the dynamic power such that transition probability xcex1inter of the inter-plane buffer 620 is larger than expected. In brief, the advantage of a Wang""s PLA lies in the AND type inter-plane buffer 620 design. However, the glitches at nodes 4 and 5 consume dynamic power. In addition, the special input circuit also increases power consumption and reduces operating speed.
A summary of all factors limiting the operating speed and the power factor of conventional dynamic PLAs is shown in Table 1 and Table 2.
Accordingly, the present invention is to provide a low power programmable logic array circuit assembly that includes an AND-plane circuit and an OR-plane circuit. The AND-plane circuit includes AND-plane dynamic gates while the OR-plane circuit includes OR-plane dynamic gates. The assembling method includes the following steps. According to the AND-plane low potential power loss when a low potential is output from the AND-plane dynamic gates, the AND-plane high potential power loss when a high potential is output from the AND-plane dynamic gates and the probability of a high potential at the AND-plane when the AND-plane dynamic gates output a high potential, a selection between AND-plane new dynamic circuit and AND-plane conventional dynamic circuit is carried out to pick up an AND-plane operating circuit for the AND-plane. Between the AND-plane dynamic gates of the AND-plane new dynamic circuit outputting a low potential and the AND-plane dynamic gates of the AND-plane conventional dynamic circuit outputting a low potential, the former has a lower transition power loss, On the contrary, between the AND-plane dynamic gates of the AND-plane new dynamic circuit outputting a high potential and the AND-plane dynamic gates of the AND-plane conventional dynamic circuit outputting a high potential, the latter has a lower transition power loss.
According to OR-plane low potential power loss when a low potential is output from the OR-plane dynamic gates, OR-plane high potential power loss when a high potential is output from the OR-plane dynamic gates and probability of a high potential at the OR-plane when the OR-plane dynamic gates output a high potential, a selection between OR-plane new dynamic circuit and OR-plane conventional footless dynamic circuit is carried out to pick up an OR-plane operating circuit for the OR-plane. Between the OR-plane dynamic gates of the OR-plane new dynamic circuit outputting a low potential and the OR-plane dynamic gates of the OR-plane conventional footless dynamic circuit outputting a low potential, the former has a lower transition power loss. On the contrary, between the OR-plane dynamic gates of the OR-plane new dynamic circuit outputting a high potential and the OR-plane dynamic gates of the OR-plane conventional footless dynamic circuit outputting a high potential, the latter has a lower transition power loss. Finally, the selected AND-plane operating circuit and the selected OR-plane operating circuit are combined to produce the low power programmable logic array.
Base on simple analysis, each type of circuit design is advantageous under a particular set of operating conditions. This invention provides an innovative complementary metal-oxide-semiconductor (CMOS) programmable logic array circuit design having a circuit selection mechanism for using the best circuit under different sets of operating conditions.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.